STEI ITB Students Win Chip Design Competition at SEACAS CHIPATON 2023

Bandung, stei.itb.ac.id – A team of students from the School of Electrical Engineering and Informatics ITB represented by two students Electrical Engineering Study Program, Fauzan Ibrahim and Nicholas Teffandi won the Award second winner in the international chip design competition, South East Asia Circuit and System Society (SEACAS) and Student Chipaton 2023. This annual event is organized by the IEEE CAS Chapter, where in 2023 it was held at the University of Philippines Diliman on September 18-19, 2023. This competition was attended by participants from 6 ASEAN countries, namely Indonesia, Singapore, Malaysia, Thailand, Vietnam, the Philippines, and Japan.

In this year's competition, the competition topic is about module design. Fast Fourier Transform (FFT)which is a digital signal processing module that is widely used in wireless communication systems (wireless communication), pemrosesan citra  (image processing) maupun pengolah suara (audio processing), dll.

In this competition, participants are asked to optimize and implement basic FFT circuits. 16-point in the form of a chip layout. The assessment criteria for determining the winner are: (1) Achievement of system performance in terms of computing speed, area and power consumption level. These performance parameters are measured in Figure of Merit (FoM) which is as small as possible; (2) Design innovation, namely the novelty or advantage of the system design compared to the basic design provided as a series of comparisons; (3) Systematic design methodology and (4) Final presentation of the design.

The STEI student team in this competition proposed an FFT design with architecture parallel radix-4 This allows for faster FFT computation times. In addition to optimization at the VLSI architecture level, the STEI team also proposed optimization at the chip implementation stage, namely by optimizing the process. floor planning And  placement-and-routingThis optimization results in a density logic cell chip which is high enough to reduce the chip area, which also corresponds to lower power consumption. During the preparation and implementation of the competition, the student team from STEI received guidance and support from a team of lecturers. Electrical Engineering Research Group that is Nana Sutisna, Ph.D And Dr. Eng. Infall Syafalni.

During the judging process, the chip design was assessed by a panel of judges consisting of representatives from each country's CAS Chapter and the IEEE ISCAS committee (General Chair and TPC Chair). In the final presentation, the STEI team was one of two teams that successfully implemented the design to the chip layout stage. This result convinced the panel of judges and they were selected as second place.

Source: Nana Sutisna, Ph.D