Publikasi Jurnal
- 2024
- 2023
- N. Sutisna, A. M. R. Ilmy, I. Syafalni, R. Mulyawan, T. Adiono, FARANE-Q: Fast Parallel and Pipeline Q-Learning Accelerator for Configurable Reinforcement Learning SoC, in IEEE Access, vol. 11, pp. 144-161, 2023, doi: 10.1109/ACCESS.2022.3232853.
- A. Satriawan, I. Syafalni, R. Mareta, I. Anshori, W. Shalannanda and A. Barra, “Conceptual Review on Number Theoretic Transform and Comprehensive Review on Its Implementations,” in IEEE Access, vol. 11, pp. 70288-70316, 2023, doi: 10.1109/ACCESS.2023.3294446.
- F. Z. Ruskanda, M. R. Abiwardani, R. Mulyawan, I. Syafalni and H. T. Larasati, “Quantum-Enhanced Support Vector Machine for Sentiment Classification,” in IEEE Access, vol. 11, pp. 87520-87532, 2023, doi: 10.1109/ACCESS.2023.3304990.
- T. Adiono, R. M. Ramadhan, N. Sutisna, I. Syafalni, R. Mulyawan and C. -H. Lin, “Fast and Scalable Multicore YOLOv3-Tiny Accelerator Using Input Stationary Systolic Architecture,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 11, pp. 1774-1787, Nov. 2023, doi: 10.1109/TVLSI.2023.3305937.
- F. Z. Ruskanda, M. R. Abiwardani, I. Syafalni, H. T. Larasati and R. Mulyawan, “Simple Sentiment Analysis Ansatz for Sentiment Classification in Quantum Natural Language Processing,” in IEEE Access, vol. 11, pp. 120612-120627, 2023, doi: 10.1109/ACCESS.2023.3327873.
- 2022
- I. Syafalni, G. Jonatan, N. Sutisna, R. Mulyawan, T. Adiono, Efficient Homomorphic Encryption Accelerator With Integrated PRNG Using Low-Cost FPGA, IEEE Access, 10, 7753-7771, 2022.
- E. Setiawan, T. Adiono, R. Mulyawan, N. Sutisna, I. Syafalni, W. O. Popoola, A Real-Time Baseband Processor for Li-Fi Internet Access, Wireless Communications and Mobile Computing, Vol 2022, Article ID 6154495, 15 pages, 2022.
- N. Sutisna, A. M. R. Ilmy, I. Syafalni, R. Mulyawan, T. Adiono, FARANE-Q: Fast Parallel and Pipeline Q-Learning Accelerator for Configurable Reinforcement Learning SoC, Techrxiv, preprint: techrxivOct2022.
- 2021
- 2017
- 2014
- 2013
- I. Syafalni, M. F. M. Salleh, Multistage A2 LVQ architecture and implementation for image compression, Digital Signal Processing, 23 (5), 1414-1426, 2013.
- I. Syafalni, T. Sasao, On the numbers of products in prefix SOPs for interval functions, IEICE TRANSACTIONS on Information and Systems, 96 (5), 1086-1094, 2013.
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