- 2023
- N Sutisna, A M R Ilmy, I Syafalni, R Mulyawan, T Adiono, FARANE-Q: Fast Parallel and Pipeline Q-Learning Accelerator for Configurable Reinforcement Learning SoC, in IEEE Access, vol. 11, pp. 144-161, 2023, doi: 10.1109/ACCESS.2022.3232853.
- A. Satriawan, I. Syafalni, R. Mareta, I. Anshori, W. Shalannanda and A. Barra, “Conceptual Review on Number Theoretic Transform and Comprehensive Review on Its Implementations,” in IEEE Access, vol. 11, pp. 70288-70316, 2023, doi: 10.1109/ACCESS.2023.3294446.
- FZ Ruskanda, MR Abiwardani, R Mulyawan, I Syafalni, HT Larasati, “Quantum-Enhanced Support Vector Machine for Sentiment Classification”, accepted in IEEE Access.
- T Adiono, RM Ramadhan, N Sutisna, I Syafalni, R Mulyawan, and C-H Lin, “Fast and Scalable Multi-Core YOLOv3-Tiny Accelerator using Input Stationary Systolic Architecture,” accepted in IEEE TVLSI.
- 2022
- I Syafalni, G Jonatan, N Sutisna, R Mulyawan, T Adiono, Efficient Homomorphic Encryption Accelerator With Integrated PRNG Using Low-Cost FPGA, IEEE Access, 10, 7753-7771, 2022.
- E Setiawan, T Adiono, R Mulyawan, N Sutisna, I Syafalni, W O Popoola, A Real-Time Baseband Processor for Li-Fi Internet Access, Wireless Communications and Mobile Computing, Vol 2022, Article ID 6154495, 15 pages, 2022.
- N Sutisna, A M R Ilmy, I Syafalni, R Mulyawan, T Adiono, FARANE-Q: Fast Parallel and Pipeline Q-Learning Accelerator for Configurable Reinforcement Learning SoC, Techrxiv, preprint: techrxivOct2022.
- 2021
- 2017
- 2014
- 2013
- I Syafalni, MFM Salleh, Multistage A2 LVQ architecture and implementation for image compression, Digital Signal Processing, 23 (5), 1414-1426, 2013.
- I Syafalni, T Sasao, On the numbers of products in prefix SOPs for interval functions, IEICE TRANSACTIONS on Information and Systems, 96 (5), 1086-1094, 2013.