Publikasi Jurnal

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  • 2022
    • I Syafalni, G Jonatan, N Sutisna, R Mulyawan, T Adiono, Efficient Homomorphic Encryption Accelerator With Integrated PRNG Using Low-Cost FPGA, IEEE Access, 10, 7753-7771, 2022.
  • 2021
    • T Adiono, A Putra, N Sutisna, I Syafalni, R Mulyawan, Low latency YOLOv3-tiny accelerator for low-cost FPGA using general matrix multiplication principle, IEEE Access, 9, 141890-141913, 2021.
  • 2017
    • I Syafalni, T Sasao, X Wen, A method to detect bit flips in a soft-error resilient TCAM, IEEE Transactions on CAD, 37 (6), 1185-1196, 2017.
  • 2014
    • I Syafalni, T Sasao, Head-tail expressions for interval functions, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 97 (10), 243-2054, 2014.
  • 2013
    • I Syafalni, MFM Salleh, Multistage A2 LVQ architecture and implementation for image compression, Digital Signal Processing, 23 (5), 1414-1426, 2013.
    • I Syafalni, T Sasao, On the numbers of products in prefix SOPs for interval functions, IEICE TRANSACTIONS on Information and Systems, 96 (5), 1086-1094, 2013.